What's happening

TSMC is developing two complementary advanced packaging technologies — Panel Level Packaging (PLP) and Chip on Panel on Substrate (CoPoS) — that replace the conventional circular wafer format with rectangular panels. CoPoS panels begin at 310×310 mm and are scalable to larger configurations such as 515×510 mm, a geometry that allows more usable surface area per production run and enables the assembly of larger, more complex chip packages suited to AI workloads. Tool deliveries for the CoPoS pilot line at TSMC's Visionchip subsidiary began in February 2026, with full line completion targeted for June 2026. Process refinement is expected to continue through 2027, with industry projections placing volume production ramp between 2028 and 2029.

The shift to panel-based packaging addresses a structural constraint in TSMC's current advanced packaging portfolio. TSMC CEO C.C. Wei, speaking on a recent earnings call, stated that 'AI demand remains exceptionally strong, and it is accelerating,' while also highlighting capacity constraints in the company's existing CoWoS (Chip on Wafer on Substrate) packaging line. CoPoS is positioned as a successor or complement to CoWoS, designed to alleviate those constraints by increasing throughput and reducing per-unit packaging costs through the more efficient use of rectangular panel geometry.

Why it matters for markets

Advanced packaging has become a critical differentiator in the AI chip supply chain, as the performance of leading-edge processors increasingly depends not only on transistor density but on how multiple chiplets and memory components are integrated at the package level. TSMC's $2.29 trillion market capitalization reflects its central role as the foundry of record for the semiconductor industry's most demanding customers, including NVIDIA — whose market capitalization stands at $5.15 trillion — and AMD, with a market capitalization of $892.36 billion. Both companies rely on TSMC's advanced packaging capabilities to bring their AI accelerator products to market, making any expansion or constraint in that capacity directly relevant to their production timelines.

The rectangular panel format at the core of CoPoS offers a measurable yield advantage over circular wafers: rectangular panels eliminate the edge waste inherent in fitting square or rectangular chip packages onto a circular substrate, increasing the number of usable package sites per production run. This efficiency gain is expected to translate into lower per-unit packaging costs, a meaningful consideration given the scale at which NVIDIA and AMD procure packaging services for data center AI products. TSMC's revenue of $4.10 trillion underscores the scale at which even incremental cost improvements in packaging yield can have material financial effects across the supply chain.

The competitive dimension is also significant. Samsung has been an active participant in advanced panel-level packaging development, and the race to establish volume production capability in this format is a direct extension of the broader foundry competition between the two companies. TSMC's decision to establish a dedicated pilot line at Visionchip, with tool deliveries already underway as of February 2026, signals a structured, phased approach to commercializing CoPoS ahead of the projected 2028–2029 volume ramp window.

Sectors and assets to watch

The primary ticker directly affected by this development is TSM (Taiwan Semiconductor Manufacturing Company), as CoPoS and PLP represent an expansion of TSMC's advanced packaging service offerings — a business segment that has grown in strategic importance alongside demand for AI accelerators. The timeline milestones — pilot line completion in June 2026, process refinement through 2027, and volume production targeted for 2028–2029 — provide a structured set of checkpoints against which TSMC's execution can be evaluated. TSMC's existing CoWoS capacity constraints, cited by CEO C.C. Wei, make the CoPoS ramp timeline particularly relevant to near-term supply chain planning.

NVDA (NVIDIA Corporation) and AMD (Advanced Micro Devices) are the most directly implicated customers, given their dependence on TSMC's advanced packaging for AI accelerator and data center GPU products. NVIDIA's data center product lines, including the A100 and H100 GPU families, and AMD's Instinct accelerator series for AI and high-performance computing, both require the kind of large, complex package integration that CoPoS is designed to enable at scale. Samsung, while not publicly traded on a U.S. exchange as a standalone entity in this context, represents the primary competitive benchmark in advanced packaging, and its progress in panel-level packaging will be a key variable in assessing TSMC's relative positioning as the 2028–2029 volume window approaches.

What to watch next

Key milestones to monitor include the completion of TSMC's CoPoS pilot line at Visionchip, targeted for June 2026, followed by any announcements regarding process qualification results or yield data emerging from that line through 2027. Investors and industry observers should also track whether TSMC provides updated guidance on CoWoS capacity expansion or CoPoS commercialization timelines in upcoming quarterly earnings calls, particularly given CEO C.C. Wei's prior comments on AI demand acceleration and packaging constraints. On the competitive side, any announcements from Samsung regarding its own panel-level packaging pilot or volume production schedules will be relevant to assessing the pace of the broader industry transition. Finally, procurement signals from NVIDIA and AMD — including any public commentary on packaging supply sufficiency for their next-generation AI accelerator roadmaps — would provide downstream confirmation of how the CoPoS ramp is being incorporated into customer planning horizons.